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tiger_programmable_logic_card

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tiger_programmable_logic_card [2019/03/12 17:24]
jon [Overview]
tiger_programmable_logic_card [2019/03/12 17:25] (current)
jon [Overview]
Line 13: Line 13:
   - Updates external I/Os with the outputs from the prior evaluation cycle ((not strictly simultaneous but within 0.3us of the trigger (had 0.3 with internal triggering, measured a bit less than 1 us with with external) ))   - Updates external I/Os with the outputs from the prior evaluation cycle ((not strictly simultaneous but within 0.3us of the trigger (had 0.3 with internal triggering, measured a bit less than 1 us with with external) ))
   - Samples all inputs synchronously ((again, not strictly synchronously but within 0.5us of the trigger))   - Samples all inputs synchronously ((again, not strictly synchronously but within 0.5us of the trigger))
-  - Computes the new outputs one cell at a time, starting with cell 1 and proceeding to cell 16. The computed outputs won't be available on the external I/Os until the start of the next evaluation cycle, but importantly the changed output of a cell can affect a later numbered cell in the same cycle. ​((If cell 2 uses the output of cell 1, there will be no apparent delay, but if cell 1 uses the output of cell 2 then it won't be updated until the next evaluation cycle.))+  - Computes the new outputs one cell at a time, starting with cell 1 and proceeding to cell 16. The computed outputs won't be available on the external I/Os until the start of the next evaluation cycle, but importantly the changed output of a cell can affect a later numbered cell in the same cycle. ​For example, if cell 2 uses the output of cell 1, there will be no apparent delay, but if cell 1 uses the output of cell 2 then it won't be updated until the next evaluation cycle.
  
 The evaluation cycle is triggered by a clock signal. By default, the evaluation clock comes from an 4kHz source on the PLC. It is also possible for the clock to be provided by another Tiger card for synchronization purposes, e.g. for diSPIM the micro-mirror card is the source of the signals being output by the PLC (e.g. camera triggers) so the micro-mirror is the master and its 4kHz clock is used to trigger PLC evaluations. Finally, the user can provide a clock on the first BNC input. The evaluation cycle is triggered by a clock signal. By default, the evaluation clock comes from an 4kHz source on the PLC. It is also possible for the clock to be provided by another Tiger card for synchronization purposes, e.g. for diSPIM the micro-mirror card is the source of the signals being output by the PLC (e.g. camera triggers) so the micro-mirror is the master and its 4kHz clock is used to trigger PLC evaluations. Finally, the user can provide a clock on the first BNC input.
tiger_programmable_logic_card.txt ยท Last modified: 2019/03/12 17:25 by jon